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SAN JOSE, Calif.--(BUSINESS WIRE)--Jan. 31, 2001--Cadence Design Systems, Inc. (NYSE:CDN), the world's leading supplier of electronic design products and services, announced the release of the Cadence® Signal Processing Worksystem (SPW) 4.6, a new version of the software that significantly increases simulation speeds. A system design tool, SPW is used in digital communications and multimedia systems such as third-generation cellular phones, digital cameras, wireless personal digital assistants, and high-definition television.

Along with increased simulation speeds, SPW 4.6 offers new polymorphic libraries, a new Global System for Mobile Communications (GSM) library with Enhanced Data Rates for Global Evolution (EDGE), improved object modeling interface (OMI) export of intellectual property (IP) to the Cadence Virtual Component Co-Design (VCC) environment, and significant documentation enhancements. In addition, SPW now has the capability to co-simulate with register transfer level (RTL) models written in SystemC 1.0 standard.

This release improves the efficiency of polymorphic model simulation for floating-point and fixed-point analysis. Significant optimizations were added to enhance generated code -- increasing simulation performance by as much as two to three times -- which makes design and verification faster for third-generation wireless systems. Creation of optimized blocks is much faster, as is simulation speed of the optimized blocks.

With SPW 4.6, the user doesn't need to change anything in existing designs or the design methodology. The widely accepted polymorphic modeling capability introduced in the previous SPW version allows more conversions from non-polymorphic to polymorphic data types.

New Libraries

New SPW 4.6 libraries include the communication library enhanced with the digital video broadcast television standard; GSM library with EDGE support for wireless Internet, Galois field blocks, and the expanded matrix library. The GSM library now includes the EDGE standard and the Enhanced General Packet Radio Service (EGPRS). The EGPRS systems models add to the already existing full-rate, half-rate, enhanced full-rate, circuit-switched data, and GPRS systems models included in the GSM library.

Object Modeling Interface Improved

SPW C-language models can be exported to VCC products. This functional model-exporting feature from SPW to VCC is enhanced, where the OMI now supports export of designs that include fixed-point signals and polymorphic signals.

Enhanced Documentation

The on-line SPW manual was expanded to include detailed examples of polymorphic modeling methods. Documentation on how to create custom C blocks was expanded with clear examples and more details about the type system, making it much easier for users not familiar with the C++ language to import C/C++ code, newly written, or legacy C/C++ models from other tools.

SystemC 1.0 Co-Simulation

SPW users have already benefited from the ability to do co-simulation with hardware description language (HDL) models written in Verilog or VHDL. This allows for simulating part of a design at the system level using SPW models and part of the system at the RTL level using HDL models. This feature is now extended to RTL models written in SystemC 1.0.

``Most designers are now waiting for SystemC to evolve into a true system language,'' said Stan Krolikoski, vice president of marketing for system-level design at Cadence. ``However, designers already using the language can immediately benefit from the new co-simulation ability of their SystemC 1.0 models with SPW. SPW/SystemC co-simulation will be very common as the language evolves and is used in flows that take it from the true system level to RTL.''

The release of this co-simulation capability underscores the Cadence commitment to support SystemC, since a standard system-level language will help both EDA vendors and its customers.

``As a charter member of the SystemC Initiative Steering Committee, STMicroelectronics is very pleased that Cadence has demonstrated its intention to adapt its tools to work with SystemC,'' said Benoit Clement, System-Level Design Engineer, Co-design Methodology for System and Architecture at STMicroelectronics.

Cadence expects to continue making its system-level tools compatible with SystemC as it evolves and will continue to play a key role in facilitating that evolution.

Pricing and Availability

SPW 4.6 is available today for UNIX-based workstations from Sun Microsystems and Hewlett-Packard. Pricing starts at $22,000 for a one-year license.

About SPW

SPW is a signal-processing-oriented design, simulation, and implementation environment for electronic systems. The SPW software is ideal for algorithm development, filter design, C-code generation, hardware/software architecture co-design, and hardware synthesis. A wide selection of polymorphic libraries is available to support communication and multimedia applications including 3G, WLAN, baseband, and physical layer processing, as well as JPEG2000 and MPEG2 standards.

About Cadence

Cadence is the largest supplier of electronic design automation products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,400 employees and 2000 annual revenue of $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services may be obtained from the World Wide Web at http://www.cadence.com.

Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. All others are properties of their owners.

     Cadence Design Systems, Inc.
     Arbella Issabey, 408/428-4456
     arbellai@cadence.com